Ter info.
Bron: X.
Kan oorspronkelijk artikel JPM effe niet linken/vinden.
Behandeld vrijwel alle technieken hier afgelopen maanden behandeld in relatie tot TSMC, AVGO, AAPL, AMD en dus ook (de relatie met) Besi.
#1
JP Morgan’s Latest Update on Advanced Packaging: Key Points on CoWoS and SoIC
Note on TSMC’s CoWoS Capacity and Demand (Including Research on Apple M5, NVIDIA GPUs, MediaTek, Google TPU, and Other ASICs)
1. CoWoS Capacity Continues to Grow Through 2027; Focus Mainly on CoWoS-L and Demand from Apple:
We expect that TSMC’s CoWoS capacity will reach 75k, 90k, and 130k wafers per month (wfpm) in 2025, 2026, and 2027 respectively, to support the demand from AI accelerators as well as emerging non-AI applications. During our forecast period, we expect TSMC to continue accounting for over 85% of the CoWoS capacity, and starting from 2025, CoWoS-L will become the main driver of capacity expansion. We believe that NVIDIA will be the primary driver of AI demand, while Apple could become a new force behind CoWoS demand as iPhone SoC packaging transitions to 2.5D packaging. Given that the migration to CoWoS-L might result in more capacity shifting back to TSMC in 2025/26, non-TSMC CoWoS capacity (e.g., from UMC) could face some challenges. We anticipate that by 2026/27, CoWoS-L will become the mainstream version, and some projects from AMD and Broadcom might follow NVIDIA in adopting CoWoS-L in 2025. By 2027, OSATs (outsourced semiconductor assembly and test companies) might regain some market share; however, with the emergence of CPO (Chip Package Optics), AI accelerators may require even closer integration with TSMC’s process. Beyond 2027, we may see TSMC consider using panel-level packaging as a way to support larger lithography sizes for its AI accelerator packaging, although this development remains in its early stages.
2. Accelerated SoIC Expansion; Slower Growth from AMD Offset by Apple M5 Demand and CPO Expectations:
We have raised our expectations for SoIC (system-in-package integration) technology, and now anticipate SoIC capacity growing to 20k and 25k wafers per month (wfpm) in 2026 and 2027 respectively. Currently, AMD is the primary user of SoIC capacity, but its demand is not expected to see strong growth over the next two years. However, Apple is likely to become a strong customer for the second-generation SoIC technology (SoIC-MH), expected to be adopted for its MacBook processors (M5 Pro, Max, possibly Ultra) starting at the end of 2025 and to be fully commercialized in 2026. We believe Apple might split its CPU and GPU into multiple chiplets and adopt an SoIC-X based integration approach combined with a passive interposer. Using a passive interposer (instead of an active interposer) could mitigate some technical challenges in the SoIC scaling process. With NVIDIA pushing for the CPO (Chip Package Optics) application in its 2027 Rubin Ultra, we expect this will further drive demand for SoIC-X, since the integration of electrical ICs and photonic ICs (EIC/PIC) requires hybrid bonding. Consequently, as NVIDIA’s CPO application timeline becomes clearer, we expect TSMC’s SoIC capacity plan may be revised upward further.
3. Rising NVIDIA Demand and Strong Migration to CoWoS-L:
Our research indicates that NVIDIA’s CoWoS demand has begun to grow, with Blackwell GPU shipments expected to reach 5.5–6.0 million units in 2025 (up from around 5.0 million previously). NVIDIA has shifted the majority of its CoWoS shipments to CoWoS-L, which might lead to very limited wafer output for CoWoS-S in the second half of 2025 (whether from TSMC or other foundries). Looking ahead to 2026, we do not expect a significant increase in NVIDIA’s CoWoS wafer output (since Rubin may adopt a similar structure comprising an N3 compute chip and eight HBM4 cubes), and compared to Blackwell, the CoWoS area required per chip may not increase much. Our current expectations for NVIDIA’s CoWoS wafer output in 2026 are slightly lower (assuming improved yields for CoWoS-L in 2026 and very low shipments of lower-spec H-series models), yet still sufficient to support roughly 8 million Blackwell/Rubin packages, compared to about 6.5 million Hopper/Blackwell packages in 2025. According to our preliminary research, we expect that by 2027, NVIDIA’s CoWoS wafer demand will grow significantly, as the integration of CPO with optical engines on the interposer layer (for Rubin Ultra) could notably increase the CoWoS package area. In addition to TSMC, we believe that ASE will see significant growth in its substrate business due to the increasing shipments of CoWoS-L from 2025 onward. We also expect that new TCB tools (such as a solderless TCB tool from KLIC currently under consideration) might be introduced for Rubin’s chip-on-wafer packaging step, potentially driving growth in the TCB supply chain. Our research further indicates signs that NVIDIA might migrate its Vera ARM CPU to CoWoS-R or a similar packaging structure (with embedded DRAM), but as this has not yet been confirmed, we have not factored it into our 2026/27 CoWoS forecasts.
4. Apple iPhone as a Key Variable for CoW Capacity from 2026 Onward, Potentially Leading to Massive CoW Demand:
Starting from 2026, we believe Apple could become a major driver of overall CoW (chip-on-wafer) capacity consumption. As noted previously (link), Apple appears to be developing a wafer-level multi-chip module (WMCM) packaging solution for its iPhone processors, where the memory chip can be packaged side-by-side with the SoC, greatly reducing the thickness and thereby aiding in improved heat dissipation (possibly to be implemented in a foldable iPhone launching in the second half of 2026). This packaging solution might require CoW capacity for chip interconnection (connecting logic and memory chips to the RDL interposer, using temporary glass carriers/substrates). We believe that a particular iPhone model might adopt this technology in the second half of 2026, with a broader rollout expected in 2027. Ultimately, this could result in very high CoW capacity demand, given the high shipment volumes and relatively large package sizes. Our observations from the supply chain suggest that Apple might reduce its InFO (integrated fan-out) packaging demand (the technology currently used for iPhone processors) in 2026 and 2027, potentially outsourcing that demand to OSAT providers as it prepares to push WMCM technology in the latter half of 2026 or in 2027. Despite the high demand, we believe that the cost of WMCM packaging could be lower than full CoWoS packaging (we estimate a per-wafer cost of $3–4k for WMCM, compared to roughly $10–12k for CoWoS wafers used in AI accelerators). Nevertheless, this would still be 2 to 2.5 times more expensive than InFO packaging.
5. TPU Migration Challenges Lead to Weaker Performance for AVGO in Early 2025, but a Strong Recovery is Expected in the Latter Half:
According to our research, Google’s migration to TPU v6 is still underway, which has resulted in relatively weak CoWoS demand in the first half of 2025. We expect that as TPU v6p is gradually promoted, demand will rebound in the second half of 2025, followed by the launch of TPU v7p. We also believe that other AVGO customers (such as ByteDance, Meta, OpenAI, etc.) are likely to significantly ramp up their demand starting in 2026. Meanwhile, as some leading XPUs (with TPU expected to be the first adopter) begin to adopt CPO technology, this will drive growth in CoWoS wafer demand, similar to the impact seen with NVIDIA’s Rubin Ultra.