#2
Die-to-wafer bonding challenges
An important layer in die-to-wafer bonding is the temporary bonding material that adheres the bottom die to the silicon wafer or glass wafer carrier.
“The temporary bonding material has a little give in it so that it can accommodate chiplets with slightly different thicknesses,” said Rama Puligadda, CTO of Brewer Science. She emphasized that the temporary bonding and release layer must have the thermal budget for all the processes of hybrid bonding or thermocompression bonding, as the case may be, then be released cleanly without residue or particles after bonding. “The temporary bonding material must be compatible with the various chemistries and high-temperature processes — as well as RDL or molding, for instance — without any die shift.” Debonding can be performed using a mechanical blade, laser, or newer pulsed UV light release.
Micron’s Zhou and colleagues determined that by replacing the organic glue it was using for temporary bonding with an inorganic film, higher thermal budgets were allowed, particulate levels were lower, and the CMP process achieved greater uniformity of copper dishing. Approximately 3 to 5nm of dishing in the planarized copper pads is needed, because copper expands relative to the dielectric during annealing.
The copper/dielectric CMP step is one of the most critical steps in the flow. It determines the flatness of the surface to be bonded (<1nm/µm roll-off is allowed). The dielectric should have a completely smooth surface (<2Å RMS roughness). Most importantly, the copper must have uniform recess levels on all copper pads.
The plasma surface activation step works to create several dangling Si-O– sites that will enable high bonding strength (>2.0 J/m2) without oxidizing the copper pads or sputtering copper onto other parts of the film or the walls of the process chamber. Samsung Electronics recently showed that a nitrogen plasma activation step, at a pressure almost 2X that of the oxygen reference plasma process, created good process conditions for SiCN films with copper pads ranging from 0.4 to 0.7µm per side (square pads). [3] The Samsung engineers used a reactive molecular dynamics simulation to determine the Ar/N2 plasma gas flows and bias power in the capacitively coupled rf reactor needed to deliver a SiCN surface that is most susceptible to bonding while minimizing copper re-sputtering.
After activation, wafers are rinsed in DI water, followed by alignment of top and bottom wafers and bonded at room temperature. Bonding strength is measured using the Maszara blade test technique. Scanning acoustic tomography is utilized to scan the bonded interface for voids, which appear as white dots on SAT images.
After bonding, the bonded wafer edges are trimmed and the top silicon wafer is ground down using silicon CMP. Wafer-edge defectivity must be tightly controlled during this CMP process.
“After wafers are bonded, a typical process is to edge trim the bonded wafer topside before grinding the top silicon substrate. It is often difficult to precisely control edge trim depth to stop at the bonding interface. After top silicon wafer partial grinding, reactive ion etching (RIE) is often used to remove the remaining silicon,” explained Kai Ma, engineering manager at Applied Materials. “If edge trim goes into the bottom wafer during RIE, etchant would create an undercut into the bottom wafer. This is because the etch-stopping dielectric layer was removed at the wafer edge during the edge trim process. If edge trim stops before reaching the bonding interface, and a Si RIE process is applied to remove post-grinding remaining silicon, then dangling membranes can form at the wafer edge bevel area, eventually becoming flake defects.” [5] The engineers found that by limiting the edge trim depth to a few microns above the bonding interface, they could remove the remaining silicon and bevel membranes, resulting in minimized edge defects.
Finally bonded chips are singulated using blade dicing, laser (stealth) dicing or plasma dicing methods. Because the top dies wafers are diced prior to placement and bonding, the singulation method must be contaminant free. “The mitigation of dicing-induced particles is obviously significant to the success of this technology. The chip-to-wafer stacking process is run in a sequential mode, which means it will take hours to complete just one memory wafer stacking,” said Zhou. In addition, even small particles can grow to create a 20X larger void at the bonding interface that prevent bonding. The Micron group decided to use laser dicing to first carve through multiple dielectric films on the streets followed by plasma dicing of the silicon bulk.
Another method engineers use to address particulate generation during processing is to deposit a protective layer, such as photoresist or other material, which is removed before the next process step.
Conclusion
The processes for hybrid bonding — including dielectric PECVD, copper ECD, CMP, plasma activation, alignment and bonding, and singulation — all involve stringent specifications for film quality, high levels of cleanliness and the assurance of known good die with high test coverage. While the industry is making great strides on integrating these processes, it will continue to pursue lower-temperature alternatives so that sensitive memories like HBM eventually can take advantage of hybrid bonding technology.